1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically to a non-volatile semiconductor memory device with a charge pump for boosting a power source voltage.
2. Description of the Related Art
Semiconductor memory devices are classified into multiple groups according to their functions. The semiconductor memory device has a memory cell array, in which multiple memory cells are arranged in a matrix. Data reading, programming or writing, and erasing operations with regard to each memory cell are generally carried out by specifying an address in a row direction and a column direction of the memory cell array.
Regulation of a voltage applied to a signal line in the row direction and to a signal line in the column direction connected to each memory cell enables an access to the memory cell, in order to carry out a predetermined operation out of the data reading, programming, and erasing operations. For selection of a certain memory cell, a specific voltage, which is different from a voltage applied to the other memory cells, is generated from a power source voltage and is applied to the certain memory cell.
Recently developed MONOS (Metal Oxide Nitride Oxide Semiconductor or Substrate)-type non-volatile semiconductor memory devices are non-volatile and enable electrical erasing of data. In the MONOS-type non-volatile semiconductor memory device, each memory cell has two memory elements as discussed in a reference Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123.
As described in this cited reference, in order to gain access to the respective memory elements in such a MONOS-type non-volatile semiconductor memory device, it is required to set a plurality of different voltages corresponding to the respective signal lines (control lines), which depend upon the number of the memory cells. Different setting voltages are also required corresponding to the respective operations (reading, programming, and erasing operations) of the memory cell.
For this purpose, multiple sets of a booster circuit, which includes a charge pump circuit driven by the power source voltage, and a regulator should be provided corresponding to the multiple setting voltages required for the respective operations of the memory cell.
The multiple sets of the booster circuit and the regulator corresponding to the multiple setting voltages required for the respective operations of the memory cell undesirably occupies a large space.
One proposed technique switches over the voltage generated by the booster circuit and the voltage generated by the regulator according to each operation mode of the memory cell.
There are a capacitor for voltage accumulation and parasitic capacitors on the output side of the booster circuit. This slows down the response of a switchover of the voltage generated by the booster circuit according to each operation of the memory cell. Especially in the case of a change from a relatively high voltage to a relatively low voltage, for example, in the case of a change from the data programming mode to the data reading mode, the operation of the charge pump circuit is stopped. Discharge of electric charges accumulated in the capacitor accordingly takes a long time. A long time period is thus required for enabling an access to the memory cell and implementing the data reading operation.
This problem is solved by newly providing a discharge circuit and a detection sensor that detects an end timing of the discharge operation. Addition of the discharge circuit and the detection sensor, however, undesirably increases the total space of the non-volatile semiconductor memory device.
The advantage of the present invention is thus to provide a non-volatile semiconductor memory device that shortens a time period required for enabling an access at the time of a switchover of an operation mode without significantly increasing the total space of the non-volatile semiconductor memory device.
In order to attain at least part of the above and the other related objects, the present invention is directed to a non-volatile semiconductor memory device having a memory cell array of multiple non-volatile memory elements. The non-volatile semiconductor memory device includes: a booster circuit that generates a boosted voltage from a power source voltage according to each of diverse operation modes in the non-volatile semiconductor memory device; a working voltage generation circuit that generates a working voltage to make a predetermined non-volatile memory element in the memory cell array carry out an operation according to each of the diverse operation modes; and a control circuit that controls operations of at least the working voltage generation circuit and the booster circuit according to each of the diverse operation modes.
The booster circuit has: a charge pump circuit that boosts the power source voltage and generates a boosted output voltage; an oscillation circuit that outputs a clock signal to control operation of the charge pump circuit; a level sense circuit that is set a relatively high first setting voltage in a first operation mode out of the diverse operation modes and a relatively low second setting voltage in a second operation mode by the control circuit, and controls operation of the oscillation circuit to make the output voltage of the charge pump circuit equal to the setting voltage; and a discharge circuit that is driven at a time of switchover from the first operation mode to the second operation mode to lower the level of the output voltage of the charge pump circuit. The level sense circuit detects a change of the output voltage of the charge pump circuit to the second setting voltage after the switchover from the first operation mode to the second operation mode, so as to detect an end timing of the operation of the discharge circuit. The control circuit stops the operation of the discharge circuit based on a result of detection of the end timing.
In the non-volatile semiconductor memory device of the present invention, the end timing of the operation of the discharge circuit is detected by the level sense circuit included in the booster circuit. This arrangement effectively shortens the time period required for enabling an access at the time of a switchover of an operation mode without significantly increasing the total space of the non-volatile semiconductor memory device.
In one preferable application, each of the non-volatile memory elements is a twin memory cell controlled by one word gate and two control gates.
This arrangement enables the memory cell array of twin memory cells to work in multiple operation modes, for example, in a data reading mode, in a data programming mode, and a in data erasing mode.
In another preferable application, each of the non-volatile memory elements has an ONO membrane including an oxide film (O), a nitride film (N), and an oxide film (O) as a trap side of electric charges.
This arrangement enables setting of a working voltage in a device using non-volatile MONOS memory cells.
The above and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiment with the accompanying drawings.